Patent Document 1 discloses a substrate noise analysis method having a step of consolidating independently of a substrate analysis structure, any of: a power supply current, a ground current, a current injected from a circuit element to a substrate, junction capacitance between a power supply, ground, a circuit element, and the substrate, interfacial resistance between the power supply, ground, a circuit element, and the substrate, power supply resistance, ground resistance, power supply voltage variation, and ground voltage variation.
Patent Document 2 discloses a substrate noise analysis method characterized by having a step of applying a static timing analysis (STA) algorithm to a description of a digital circuit and generating timing information related to one or more gates in the digital circuit, a step of applying an electrical current waveform generation (CWG) algorithm to the description of the digital circuit and a description of the timing information concerning one or more gates in the digital circuit and a switching operation of the digital circuit, and generating an electrical current waveform, and a step of generating a reduced model (RM) for simulation of the digital circuit, according to a model of a package related to the electrical current waveform and the digital circuit, and of generating a noise index for a substrate related to the digital circuit, by the RM simulation of the digital circuit.
Furthermore, Non-Patent Document 1 discloses a method of simulating, with high precision, substrate noise that affects performance of an analog circuit disposed in the same substrate, by creating a macro-model with primitive instance units. Here, the (primitive) instance indicates a name for uniquely distinguishing a cell specifying a logical unit within the substrate.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2005-4245A
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2006-236340A
[Non-Patent Document 1]
Marc van Heijningen et. al., “High-Level Simulation of Substrate Noise Generation Including Power Supply Noise Coupling”, 2000 DAC, FIG. 1.